At least some interconnections in integrated circuits are made by strip-like metallic conductors that are formed by patterning a deposited metal film. As the technology of integrated circuits evolves toward higher circuit densities, circuit designs call for decreasing both the widths of such metal interconnections, and the spacings between them.
One parameter for describing the geometrical configuration of an intermetallic spacing is the aspect ratio, i.e., the height of the metal film divided by the distance between the adjacent strip-like conductors that define the spacing. Although conventional spacings are substantially greater than 1 .mu.m in width and have an aspect ratio substantially less than 1, newer circuit designs call for spacings of 1 .mu.m or even less, and for aspect ratios of 1 or more.
Conventionally, the patterned metallic layers that represent such interconnections are overcoated with a layer of dielectric material, typically a silicon oxide material. (Additional metal interconnections may be formed by patterning a metallic layer deposited above such a dielectric layer. In such a case, the dielectric layer is referred to as an "interlevel dielectric film.")
To be effective, the dielectric coating must fill the intermetallic spacings substantially without defects. Two important classes of defects have been identified; they are "soft spots" and "key holes." A soft spot is a low-density region of the dielectric coating, and it is formed where the rate of ion bombardment is reduced by the shadowing effect of the shoulders of the metallic conductor pattern. A key hole is a void in the dielectric coating, and it is formed when shadowing is so severe that dielectric is prevented from depositing within the intermetallic region, while the dielectric deposited on the shoulder regions bounding the intermetallic region grow fast enough to merge above the void.
As aspect ratios increase, it becomes more difficult to deposit dielectric layers such that the intermetallic spacings are filled substantially without soft spots and key holes. This is because shadowing effects become more severe at higher aspect ratios. Various deposition methods have been proposed for forming dielectric layers, such as intermetallic dielectric films, to fill metallic interconnections having aspect ratios of one or greater. For example, the use of radio-frequency (RF) bias sputtering to deposit silicon dioxide films was reported by C. Y. Ting, et al., J. Vac. Sci. Technol., 15, (1978), p. 1105, T. Mogami, et al., J. Vac. Sci. Technol., B3, (1985), p. 857, and B. Singh, et al., J. Vac. Sci. Technol. B5, (1987), p. 567. However, commercial applications of this method may be limited because the method currently achieves a deposition rate of less than 200 .ANG./minute, whereas commercial applications typically require deposition rates greater than 1000 .ANG./minute for single-wafer reactors, or 500 .ANG./minute (depending on the number of wafers processed at one time) for multiple-wafer reactors. Another method, bias electron cyclotron resonance plasma deposition, has been described, for example, by K. Muchida, et al., J. Vac. Sci. Technol., B4, (1986), p. 818. However, problems associated with thickness non-uniformity and particulate contamination have not been completely solved for this method. Yet another method, plasma enhanced chemical vapor deposition (PECVD) using TEOS (tetraethyl orthosilicate) precursor has been described, for example, by B. L. Chin, et al., Solid State Technol., (April 1988), p. 119. This method is the method most widely adopted for depositing interlevel silicon dioxide films. However, it is generally unfeasible to deposit high-quality dielectrics by this method in intermetallic spacings having aspect ratios greater than about 0.8.
Another application of PECVD for forming silicon dioxide layers is described in U.S. Pat. No. 4,681,653, issued to Purdes, et al. on Jul. 21, 1987. Purdes used silane and nitrous oxide precursors to deposit planarizing silicon dioxide films. A very large substrate bias of -900 volts provided a large back-sputtering yield to planarize the film. However, the high substrate bias used with this technique may result in radiation damage that can harm device performance.
Thus, practitioners in the art have so far sought, without success, a method for forming, over high-aspect-ratio metallization patterns, silicon dioxide films of excellent quality (i.e., that are substantially free of soft spots and key holes) that is relatively fast and that is free of potential problems due to radiation damage, thickness non-uniformity, and particulate contamination.